The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2025

Filed:

Jun. 27, 2023
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Rishabh Kaistha, Nangal, IN;

Akhil Garg, Greater Noida, IN;

Kunal Singh Sengar, Bikaner, IN;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/037 (2006.01); H03K 19/003 (2006.01); H03K 19/21 (2006.01);
U.S. Cl.
CPC ...
H03K 3/0375 (2013.01); H03K 3/0372 (2013.01); H03K 19/00338 (2013.01); H03K 19/21 (2013.01);
Abstract

A single event upset (SEU) hardened flip-flop comprises a master latch and a plurality of slave latches, where an output of the master latch is coupled to a respective input of the slave latches. A Muller element which has an input which is coupled to a respective output of the slave latches and an output which is coupled to a bus keeper. The bus keeper maintains a logic level output in presence of the SEU.


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