The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2025

Filed:

Sep. 15, 2022
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Ranadeep Dutta, Del Mar, CA (US);

Abdellatif Bellaouar, Richardson, TX (US);

Chuan-Cheng Cheng, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03F 1/26 (2006.01); H03F 3/45 (2006.01);
U.S. Cl.
CPC ...
H03F 1/26 (2013.01); H03F 3/45475 (2013.01); H03F 2200/372 (2013.01);
Abstract

An apparatus is disclosed for reducing parasitic capacitance. In an example aspect, an apparatus includes an amplifier having a differential cascode configuration. Each stack of the amplifier includes a first transistor configured to operate as an input stage and a second transistor configured to operate as a cascode stage. The first and second transistors each include two channel terminal regions having a doping type that is uniform across the two channel terminal regions. Surfaces of first channel terminal regions of the first and second transistors abut a first and second quantity of electrical contacts, respectively. Second channel terminal regions of the first and second transistors form a floating region at a floating node. Each of the first quantity of electrical contacts and the second quantity of electrical contacts is greater than a third quantity of electrical contacts abutting a surface of the floating region.


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