The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2025

Filed:

Oct. 06, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventor:

Hyejin Kim, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/36 (2006.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 23/36 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 24/73 (2013.01); H01L 2223/54426 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/2929 (2013.01); H01L 2224/29386 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01);
Abstract

A package substrate includes at least one substrate base, a plurality of wiring patterns disposed on an upper surface and a lower surface of the at least one substrate base and extending in a horizontal direction, a plurality of wiring vias extending in a vertical direction through the at least one substrate base and electrically connecting two wiring patterns positioned at different vertical levels among the plurality of wiring patterns, to each other, and an upper surface solder resist layer having a plurality of first upper surface openings extending from the upper surface to the lower surface, and at least two upper surface openings having a second opening width as a horizontal width that is greater than a first opening width which is a horizontal width of the plurality of first upper surface openings, the upper surface solder resist layer covering an upper surface of the at least one substrate base.


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