The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2025

Filed:

Mar. 13, 2023
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Dmitri Yudanov, Santa Clara, CA (US);

Michael Ignatowski, Austin, TX (US);

Assignee:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 13/16 (2006.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01); G11C 5/14 (2006.01); G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 29/02 (2006.01); G11C 29/30 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4068 (2013.01); G06F 13/1668 (2013.01); G11C 5/02 (2013.01); G11C 5/06 (2013.01); G11C 5/147 (2013.01); G11C 7/06 (2013.01); G11C 29/30 (2013.01); G11C 29/44 (2013.01); G11C 7/1012 (2013.01); G11C 29/025 (2013.01);
Abstract

An apparatus and method for performing memory operations in memory stacks comprising receiving a memory operation request at a first memory controller, where the first memory controller is in included in a first logic die in communication with a first memory die of a first memory technology, from a processor via a first bus. The method further comprising, on a condition that the memory operation request is associated with a second memory technology, communicating the memory operation request to a second memory controller via a side bus, where the second memory controller is included in a second logic die in communication with a second memory die of the second memory technology, and, on a condition that the memory operation request is associated with the first memory technology, performing the memory operation request. The first and second logic dies and the first and second memory dies being stacked on the processor.


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