The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2025

Filed:

Jul. 03, 2024
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:
Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01); G06F 21/45 (2013.01);
U.S. Cl.
CPC ...
G06F 13/4027 (2013.01); G06F 13/1668 (2013.01); G06F 13/4282 (2013.01); G06F 21/45 (2013.01); G06F 2213/0026 (2013.01);
Abstract

Examples systems are provided for isolating transactions originating from different types of applications, including systems for providing such isolation on an inbound side and systems for providing such isolation on an outbound side, as well as end-to-end isolation systems. Such systems may be implemented in a peripheral component interconnect express (PCIe) environment. On an outbound side, a first interconnect receives transactions having different attributes indicating different application origins, respectively, and selects different pathways for the transactions based on their respective attributes. On an inbound side, a second interconnect selects different pathways for the transactions based on their respective attributes. Thus, transactions originating from safety and non-safety applications may be kept isolated as they are routed, and a non-safety transaction may be restricted from accessing certain portions of memory.


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