The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2025

Filed:

Feb. 28, 2024
Applicant:

Silicon Laboratories Inc., Austin, TX (US);

Inventors:

Paul Zavalney, Austin, TX (US);

Rejoy Roy Mathews, Austin, TX (US);

Adrianus Bink, Oslo, NO;

Assignee:

Silicon Laboratories Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1626 (2013.01); G06F 13/1663 (2013.01);
Abstract

In one embodiment, an apparatus includes: a fabric circuit to couple between a plurality of managers and a memory; and multi-bank memory control circuitry coupled to the fabric circuit and to couple to a plurality of banks of the memory and including a plurality of first ports to receive memory requests from the plurality of managers, The multi-bank memory control circuitry is to enable each of the plurality of managers to access the memory in parallel. A global monitor is coupled to the multi-bank memory control circuitry and includes a plurality of second ports and a plurality of state machines, each of the plurality of state machines to be associated with one of the plurality of managers. Each of the plurality of state machines is configured to enforce exclusivity of a memory region on behalf of a manager and concurrently enable non-exclusive access to the memory region.


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