The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2025

Filed:

May. 10, 2023
Applicant:

SK Hynix Inc., Icheon-si Gyeonggi-do, KR;

Inventor:

Young Ock Hong, Icheon-si Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Icheon-si Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 25/065 (2023.01); H10B 80/00 (2023.01);
U.S. Cl.
CPC ...
G01R 31/2884 (2013.01); H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 25/0657 (2013.01); H10B 80/00 (2023.02); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2225/06565 (2013.01); H01L 2924/1437 (2013.01);
Abstract

There is provided a semiconductor device having a defect detection circuit. The semiconductor device includes a plurality of upper bonding pads, a plurality of lower bonding pads adhered to the plurality of upper bonding pads, a first upper line electrically connecting upper bonding pads, among the plurality of upper bonding pads, to each other; a plurality of lower lines electrically connected to the plurality of lower bonding pads; and a first defect detection circuit including an input terminal connected to a lower line, among the plurality of lower lines and an output terminal connected to another lower line, among the plurality of lower lines.


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