The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2025

Filed:

Feb. 06, 2020
Applicant:

Lam Research Corporation, Fremont, CA (US);

Inventors:

Michael John Martin, Union City, CA (US);

Yuhou Wang, Fremont, CA (US);

Alexander Miller Paterson, San Jose, CA (US);

Assignee:

Lam Research Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B25J 9/16 (2006.01); B25J 11/00 (2006.01); B25J 13/08 (2006.01); H01J 37/32 (2006.01); H01L 21/68 (2006.01); H01L 21/683 (2006.01); H01L 21/687 (2006.01);
U.S. Cl.
CPC ...
B25J 9/1697 (2013.01); B25J 11/0095 (2013.01); B25J 13/08 (2013.01); H01J 37/32733 (2013.01); H01L 21/681 (2013.01); H01J 2237/206 (2013.01); H01J 2237/334 (2013.01); H01L 21/6831 (2013.01); H01L 21/68707 (2013.01); H01L 21/68721 (2013.01);
Abstract

Systems and methods are provided for positioning a wafer in relation to a datum structure. In one example, a system comprises a camera arrangement including at least two cameras, each of the at least two cameras including a field of view when positioned in the camera arrangement, each field of view including a peripheral edge of the wafer and a peripheral edge of the datum structure. A processor receives positional data from each of the at least two cameras and determines, in relation to each field of view, a gap size between the respective peripheral edges of the wafer and the datum location included in the respective field of view. A controller adjusts a position of the wafer relative to the datum structure based on the determined respective gap sizes.


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