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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12396334 B1

PDFFull Text
Date of Patent:
Aug. 19, 2025

Filed:

Nov. 17, 2020

Display apparatus and method of manufacturing the same

Applicant:

Samsung Display Co., Ltd., Yongin-Si, KR;

Inventors:

Won Je Jo, Ansan-si, KR;

Young Ji Kim, Hwaseong-si, KR;

Yi Seul Um, Chungcheongnam-do, KR;

Young Hoon Lee, Gwangmyeong-si, KR;

Seong Geun Won, Hwaseong-si, KR;

Young Seo Choi, Yongin-si, KR;

Hyun Min Hwang, Seoul, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Gyeonggi-Do, KR;

Attorney:

CANTOR COLBURN LLP

Primary Examiner:

Dzung Tran

Int. Cl.
CPC ...
H01L 27/32 (2006.01); H10K 50/844 (2023.01); H10K 50/87 (2023.01); H10K 59/122 (2023.01); H10K 59/124 (2023.01); H10K 59/80 (2023.01); H10K 71/00 (2023.01); H10K 59/12 (2023.01); H10K 59/65 (2023.01);
U.S. Cl.
CPC ...
H10K 59/124 (2023.02); H10K 50/844 (2023.02); H10K 50/87 (2023.02); H10K 59/122 (2023.02); H10K 59/8794 (2023.02); H10K 71/00 (2023.02); H10K 59/1201 (2023.02); H10K 59/65 (2023.02); H10K 59/8731 (2023.02);
Abstract

A display apparatus includes a base substrate including a hole area through which light passes, a hole peripheral area which is a non-display area surrounding the hole area, and a display area surrounding the hole peripheral area, where the display area includes pixels to display an image, an insulating layer disposed on the base substrate in the hole peripheral area and the display area except for the hole area, a via insulating layer disposed on the insulating layer in the hole peripheral area and the display area except for the hole area, and a thin film encapsulation layer including first and second inorganic films which are disposed in the hole peripheral area and the display area except for the hole area on the base substrate on which the via insulating layer is disposed.

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