The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

Apr. 13, 2021
Applicant:

Meta Platforms Technologies, Llc, Menlo Park, CA (US);

Inventor:

Rajendra D. Pendse, Fremont, CA (US);

Assignee:

Meta Platforms Technologies, LLC, Menlo Park, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10H 20/857 (2025.01); H01L 25/075 (2006.01); H10H 20/01 (2025.01); H10H 20/852 (2025.01);
U.S. Cl.
CPC ...
H10H 20/857 (2025.01); H01L 25/0753 (2013.01); H10H 20/852 (2025.01); H10H 20/0362 (2025.01); H10H 20/0364 (2025.01);
Abstract

An article including a semiconductor die including integrated circuitry is described. The semiconductor die defines a first major surface, a second major surface opposite the first major surface, and a plurality of perimeter walls joining the first major surface and the second major surface. The article further includes at least one through silicon via extending through the semiconductor die between the first major surface and the second major surface and a fill material surrounding at least part of the semiconductor die. The fill material contacts at least one of the plurality of perimeter walls, and a surface of the fill material is substantially co-planar with the first major surface of the semiconductor die. The article further includes at least one redistribution layer on the first major surface of the semiconductor die and the surface of the fill material.


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