The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

Oct. 18, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Junhyoung Kim, Seoul, KR;

Seungmin Lee, Seoul, KR;

Sangbeom Han, Seoul, KR;

Joonsung Lim, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/40 (2023.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/20 (2023.01); H10B 41/35 (2023.01); H10B 41/40 (2023.01); H10B 43/10 (2023.01); H10B 43/20 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H10B 43/40 (2023.02); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/20 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/10 (2023.02); H10B 43/20 (2023.02); H10B 43/35 (2023.02);
Abstract

A semiconductor device includes a stack structure including a gate stack region and dummy stack region. The gate stack region includes interlayer insulating layers and gate electrodes alternately stacked. The dummy stack region includes dummy insulating layers and dummy horizontal layers alternately stacked. A separation structure penetrates the stack structure. A vertical memory structure penetrates the gate stack region in a first region. A plurality of gate contact structures electrically connect to the gate electrodes in a second region. The gate electrodes include a first gate electrode and a second gate electrode disposed on a level higher than the first gate electrode. Each of the gate contact structures includes a gate contact plug and a first insulating spacer. The gate contact plugs include a first gate contact plug penetrating the second gate electrode and contacting the first gate electrode, and a second gate contact plug contacting the second gate electrode.


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