Computer architecture with data decompression support for neural network computing

Abstract

A processor decompresses a compressed data vector into an original data vector. The processor includes an execution circuit, which receives a decompress instruction that includes two input operands and an output operand. The input operands indicate an address of the compressed data vector in a memory, and the output operand indicates the vector register for storing the original data vector after decompression. The execution circuit executes the decompress instruction to decompress the compressed data vector. When executing the decompress instruction, the execution circuit performs the following operations: read a mask value from the mask register, the mask value being a binary sequence indicating zero positions in the original data vector; generate a selection signal based on the mask value; and generate the original data vector by applying the selection signal to a selection switch that receives the compressed data vector as input.