The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

Sep. 15, 2023
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Kirill Trunov, Warstein, DE;

Waltraud Eisenbeil, Großostheim, DE;

Frederick Groepper, Paderborn, DE;

Joerg Schadewald, Warstein, DE;

Arthur Unrau, Geseke, DE;

Ulrich Wilke, Soest, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/16 (2023.01); B23K 1/19 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/373 (2006.01); H01L 23/488 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/07 (2006.01); H05K 3/34 (2006.01); B23K 1/00 (2006.01); H05K 3/12 (2006.01);
U.S. Cl.
CPC ...
H01L 25/16 (2013.01); H01L 21/4853 (2013.01); H01L 23/49811 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 24/97 (2013.01); H01L 2224/32227 (2013.01); H01L 2224/32507 (2013.01); H01L 2224/8381 (2013.01); H01L 2224/83815 (2013.01);
Abstract

An electronic device includes a substrate including first and second metal regions, a first passive device that includes a metal joining surface and is arranged on the substrate with the metal joining surface of the first passive device facing first metal region, a semiconductor die that includes a metal joining surface and is arranged on the substrate with the metal joining surface of the semiconductor die facing the second metal region, a first soldered joint between the metal joining surface of the first passive device and the first metal region; and a second soldered joint between the metal joining surface of the semiconductor die and the second metal region, wherein a minimum thickness of the first soldered joint is greater than a maximum thickness of the second soldered joint.


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