The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 19, 2025
Filed:
Aug. 15, 2022
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Prakash Rattaisutripalayam Palanisamy, Bangalore, IN;
Bruce Lee, Irvine, CA (US);
Bavireddy Sai Krishna, Guntur, IN;
Balavva Shivappa Kamatagi, Bailhongal, IN;
Assignee:
QUALCOMM INCORPORATED, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10D 1/68 (2025.01); H10D 84/80 (2025.01);
U.S. Cl.
CPC ...
H01L 23/5223 (2013.01); H01L 23/528 (2013.01); H10D 1/714 (2025.01); H10D 84/813 (2025.01);
Abstract
A chip includes a first capacitor. The first capacitor includes first electrodes formed from metal layer M0, wherein the first electrodes are coupled to one another. The first capacitor also includes second electrodes formed from the metal layer M0, wherein the second electrodes are coupled to one another.
Rattaisutripalayam Palanisamy, Prakash. (2025). Layout design of custom stack capacitor to procure high capacitance (U.S. Patent No. 12394705). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12394705
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile