The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

Dec. 18, 2023
Applicant:

Commissariat À L'énergie Atomique ET Aux Énergies Alternatives, Paris, FR;

Inventors:

Baptiste Jadot, Gif sur Yvette, FR;

Gérard Billiot, Gif sur Yvette, FR;

Yvain Thonnart, Gif sur Yvette, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 10/40 (2022.01); G06N 3/065 (2023.01); G06N 10/00 (2022.01); G11C 7/10 (2006.01); G11C 27/02 (2006.01); H03M 1/82 (2006.01);
U.S. Cl.
CPC ...
G06N 10/40 (2022.01); G06N 3/065 (2023.01); G06N 10/00 (2019.01); G11C 7/10 (2013.01); G11C 27/024 (2013.01); H03M 1/82 (2013.01);
Abstract

The circuit is connected to the quantum circuit by bias lines and includes a digital-to-analog converter—DAC delivering an analog voltage; memory cells, connected in parallel at the output of the DAC, each memory cell including a switch and a capacitor, the capacitor storing a level of potential at which to maintain a bias line connected to the output of the memory cell; and a device for generating control signals generating, in synchronization with the DAC, a control signal for each switch of each memory cell, the control signal, a value of the capacitor of a memory cell being selected so as to make negligible a parasitic capacitor affecting the bias line connected to the memory cell and which runs parallel to a neighboring bias line.


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