The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 19, 2025

Filed:

Jun. 20, 2023
Applicant:

Semiconductor Components Industries, Llc, Scottsdale, AZ (US);

Inventor:

Ivo Leonardus Coenen, Coffrane, CH;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/3296 (2019.01); G06F 1/08 (2006.01); G06F 1/324 (2019.01);
U.S. Cl.
CPC ...
G06F 1/3296 (2013.01); G06F 1/08 (2013.01); G06F 1/324 (2013.01);
Abstract

Integrated circuits on semiconductor substrates and methods for operating integrated circuits on semiconductor substrates. The method includes adjusting a clock signal, generated by a clock circuit, from a first frequency to a second frequency. The method also includes adjusting a digital supply voltage, generated by a digital supply voltage converter, to a predetermined maximum value for the second frequency. The method further includes adjusting a body biasing voltage, generated by a body voltage converter, to a predetermined value for the second frequency. The method also includes determining, by a controller, speed margins based on logic speed measurements from a logic gate delay line. The method further includes decreasing the digital supply voltage until the speed margins are less than a predetermined threshold margin. The clock circuit, the digital supply voltage converter, the body voltage converter, the controller, and the logic gate delay line are implemented on the semiconductor substrate.


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