The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

Nov. 13, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventor:

Effendi Leobandung, Stormville, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10N 70/00 (2023.01); H10B 63/00 (2023.01); H10N 70/20 (2023.01);
U.S. Cl.
CPC ...
H10N 70/068 (2023.02); H10B 63/30 (2023.02); H10B 63/80 (2023.02); H10N 70/231 (2023.02); H10N 70/826 (2023.02); H10N 70/8413 (2023.02);
Abstract

Various methods and structures for fabricating a semiconductor structure with vertical vias interconnecting BEOL metallization layers. A first BEOL metallization layer includes a first metallization contact. A second BEOL metallization layer is disposed on the first BEOL metallization layer. The second BEOL metallization layer includes a second metallization contact. A dielectric layer is vertically interposed between the first and second metallization layers. A first vertical via interconnects, through the dielectric layer, the first and second metallization contacts. In the first vertical via, a phase change material non-volatile memory (PCM) is vertically interposed between an upper electrode and a lower electrode. The lower electrode is electrically connected to the first metallization contact. The upper electrode is electrically connected to the second metallization contact.


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