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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12389761 B1

PDFFull Text
Date of Patent:
Aug. 12, 2025

Filed:

Apr. 03, 2024

Display device

Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Sanghyun Lim, Paju-si, KR;

Minji Kang, Paju-si, KR;

Sehwan Na, Paju-si, KR;

Assignee:

LG DISPLAY CO., LTD., Seoul, KR;

Attorney:

Birch, Stewart, Kolasch & Birch, LLP

Primary Examiner:

Mariceli Santiago

Int. Cl.
CPC ...
H10K 50/844 (2023.01); H04N 23/54 (2023.01); H10K 59/00 (2023.01); H10K 59/122 (2023.01); H10K 59/124 (2023.01); H10K 59/131 (2023.01); H10K 59/65 (2023.01); H10K 59/80 (2023.01); H10K 77/10 (2023.01);
U.S. Cl.
CPC ...
H10K 59/124 (2023.02); H04N 23/54 (2023.01); H10K 50/844 (2023.02); H10K 59/00 (2023.02); H10K 59/122 (2023.02); H10K 59/131 (2023.02); H10K 77/10 (2023.02); H10K 59/65 (2023.02); H10K 59/8731 (2023.02);
Abstract

Discussed is a display device including an organic light emitting device in a display area on a substrate, a thin film transistor connected with the organic light emitting device, a planarization layer on the thin film transistor, a protecting portion on a buffer area on the substrate, the protecting portion surrounding at least a portion of a camera area on the substrate, the buffer area disposed between the display area and the camera area, a dam structure on the buffer area, the dam structure apart from the protecting portion, an encapsulation layer including a first encapsulation layer, a second encapsulation layer on the first encapsulation layer, and a third encapsulation layer on the second encapsulation layer, and a hole in the camera area, the hole provided inside the display area. The first encapsulation layer and the third encapsulation layer are disposed on a side surface of the planarization layer.

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