The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 12, 2025
Filed:
Dec. 16, 2021
Applicant:
Stmicroelectronics S.r.l., Agrate Brianza, IT;
Inventor:
Davide Giuseppe Patti, Mascalucia, IT;
Assignee:
STMicroelectronics S.r.l., Agrate Brianza, IT;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/01 (2025.01); H01L 21/225 (2006.01); H01L 21/265 (2006.01); H10D 30/66 (2025.01); H10D 62/17 (2025.01); H10D 64/00 (2025.01); H01L 21/765 (2006.01);
U.S. Cl.
CPC ...
H10D 30/0297 (2025.01); H01L 21/2253 (2013.01); H01L 21/2652 (2013.01); H01L 21/26586 (2013.01); H10D 30/668 (2025.01); H10D 62/393 (2025.01); H10D 64/117 (2025.01); H01L 21/765 (2013.01);
Abstract
A process is proposed for manufacturing an integrated device having at least one MOS transistor integrated on a die of semiconductor material. The process includes forming one or more gate trenches with corresponding field plates and gate regions. A body region is formed by implanting dopants selectively along one or more implantation directions that are tilted with respect to a front surface of the die. Moreover, a corresponding integrated device and a system comprising this integrated device are proposed.