The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

Sep. 15, 2023
Applicant:

Montage Technology (Kunshan) Co., Ltd., Jiangsu, CN;

Inventors:

Kang Wei, Suzhou, CN;

Jinfu Chen, Suzhou, CN;

Liang Zhang, Suzhou, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/017 (2006.01); H03K 3/011 (2006.01); H03K 5/135 (2006.01); H03K 5/156 (2006.01);
U.S. Cl.
CPC ...
H03K 3/017 (2013.01); H03K 3/011 (2013.01); H03K 5/135 (2013.01); H03K 5/1565 (2013.01);
Abstract

A duty cycle calibration circuit includes delay, temperature compensation, differential, and phase adjustment units. The delay adjustment unit receives a single-ended input clock signal to be calibrated and an adjustment voltage and outputs a single-ended clock signal adjusted by the adjustment voltage. The temperature compensation adjustment unit determines the adjustment voltage output by the temperature compensation adjustment unit, and provides the adjustment voltage to the delay adjustment unit to eliminate the influence of the temperature on the duty cycle. The differential adjustment unit converts the single-ended clock signal into a differential clock signal, and adjusts delay of the differential clock signal. The phase adjustment unit receives the adjusted differential clock signal to adjust its phase and converts it into a single-ended output clock signal after phase adjustment, and makes rising and falling edges of the single-ended output clock signal correspond to rising edges of the adjusted differential clock signal respectively.


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