The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

Jun. 23, 2023
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Seokkyun Ko, San Diego, CA (US);

Ashwin Sethuram, San Clemente, CA (US);

Jeffrey Mark Hinrichs, San Diego, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 7/08 (2006.01); H03K 3/017 (2006.01); H03K 19/173 (2006.01); H03K 19/20 (2006.01); H04B 1/16 (2006.01);
U.S. Cl.
CPC ...
H03K 3/017 (2013.01); H03K 7/08 (2013.01); H03K 19/1737 (2013.01); H03K 19/20 (2013.01); H04B 1/16 (2013.01);
Abstract

A data signal receiver circuit, including: a comparator configured to generate a first data signal based on a comparison of an input data signal and a reference voltage, wherein the first data signal includes a first logic low pulse and a first logic high pulse; and a duty cycle control circuit configured to generate: a second data signal based on the first data signal, wherein the second data signal includes a second logic low pulse responsive to the first logic low pulse, wherein the second logic low pulse has a width greater than a unit interval (UI); and a third data signal based on the first data signal, wherein the third data signal includes a second logic high pulse responsive to the first logic high pulse, wherein the second logic high pulse has a width greater than the UL.


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