The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

Feb. 27, 2023
Applicant:

Toyota Motor Engineering & Manufacturing North America, Inc., Plano, TX (US);

Inventors:

Feng Zhou, Ann Arbor, MI (US);

Tianzhu Fan, Houston, TX (US);

Yanghe Liu, Ann Arbor, MI (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/42 (2006.01); H01L 23/00 (2006.01); H01L 23/427 (2006.01); H05K 1/02 (2006.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H01L 23/427 (2013.01); H01L 24/32 (2013.01); H05K 1/0203 (2013.01); H05K 1/185 (2013.01); H01L 2224/32221 (2013.01); H01L 2924/1011 (2013.01); H05K 2201/064 (2013.01); H05K 2201/10007 (2013.01);
Abstract

A power device embedded printed circuit board (PCB) assembly includes a cold plate, a multi-layer PCB with at least one power device embedded therein bonded to and in thermal communication with the cold plate, and a chemical vapor deposition (CVD) dielectric layer disposed between the cold plate and the multi-layer PCB. The CVD dielectric layer can be applied to the cold plate and a bonding layer can be sandwiched between the CVD dielectric layer and the multi-layer PCB with at least one power device assembly embedded therein. In the alternative, CVD dielectric layer can be applied top the multi-layer PCB with at least one power device assembly embedded therein and bonding layer can be sandwiched between the CVD dielectric layer and the cold plate.


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