The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

Feb. 14, 2023
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

David Tran, San Jose, CA (US);

Federico Venini, San Jose, CA (US);

Sarosh I. Azad, Fremont, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 29/02 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G11C 29/52 (2013.01); G11C 29/022 (2013.01);
Abstract

A memory system that splits a data width (W) into N separate memories each of narrower width W/N is described. To protect a write enable (WE) signal, the WE signal is toggled and then stored in each of the N memories. A fault on the WE signal to any of the N memories results in its stored write detection bit being different from the write detection bits stored in the other N memories. This condition can then be detected upon any subsequent read by checking whether the write detection bits are equal. The memory system can also protect the address and control signals by generating parity bits that are stored in the N memories.


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