Memory device, system and method employing multiphase clock

Abstract

A memory device includes a DC conversion circuit that receives a first edge-triggered phase signal having first pulses each extending from a rising edge of a first phase signal of a multiphase clock to a later rising edge of a second phase signal of the multiphase clock and a second edge-triggered phase signal having second pulses each extending from a rising edge of the second phase signal to a later rising edge of the first phase signal, and outputting a first voltage corresponding to the first edge-triggered phase signal and a second voltage corresponding to the second edge-triggered phase signal, a comparator that compares the first voltage with the second voltage, control logic that generates a control code corresponding to an output value from the comparator, and a delay cell that delays the second phase signal according to the control code.