The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

Dec. 02, 2020
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Susumu Kawashima, Atsugi, JP;

Manabu Sato, Oyama, JP;

Koji Kusunoki, Isehara, JP;

Hidenori Mori, Kawachi, JP;

Hironori Matsumoto, Tochigi, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 19/28 (2006.01); G09G 3/3266 (2016.01); G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
G11C 19/28 (2013.01); G09G 3/3266 (2013.01); G09G 3/3677 (2013.01); G09G 2310/0286 (2013.01);
Abstract

A highly reliable semiconductor device is provided. The semiconductor device includes first to third transistors and a capacitor. In the first transistor, one of a source and a drain is supplied with a first signal, the other of the source and the drain is connected to a gate of the second transistor and one electrode of the capacitor, and a gate is supplied with a second pulse signal. In the second transistor, one of a source and a drain is supplied with a first pulse signal, and the other of the source and the drain is connected to the other electrode of the capacitor and one of a source and a drain of the third transistor. In the third transistor, the other of the source and the drain is supplied with the first potential, and a gate is supplied with a second signal that is an inverted signal of the first signal. The first pulse signal is a clock signal, and the second pulse signal has a duty ratio of 55% or lower.


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