The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

Oct. 06, 2023
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Yoshihiko Kamata, Yokohama, JP;

Naofumi Abiko, Kawasaki, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 7/12 (2006.01); G11C 11/4094 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/32 (2006.01); G11C 16/34 (2006.01); G11C 7/18 (2006.01); G11C 8/08 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3445 (2013.01); G11C 7/12 (2013.01); G11C 11/4094 (2013.01); G11C 11/5635 (2013.01); G11C 16/0475 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01); G11C 16/3459 (2013.01); G11C 7/18 (2013.01); G11C 8/08 (2013.01); G11C 2211/5641 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes first and second memory cells, a first word line, first and second sense amplifiers, first and second bit lines, a controller. The first and second sense amplifiers each include first and second transistors. The first bit line is connected between the first memory cell and the first transistor. The second bit line is connected between the second memory cell and the second transistor. In the read operation, the controller is configured to apply a kick voltage to the first word line before applying the read voltage to the first word line, and to apply a first voltage to a gate of the first transistor and a second voltage to a gate of the second transistor while applying the kick voltage to the first word line.


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