Memory device and operating method thereof

Abstract

A memory device comprises: a memory cell array including a plurality of cell blocks including a first cell block storing information other than user data and a second cell block storing the user data, wherein each of the plurality of cell blocks includes a plurality of cell strings and control circuitry configured to control a write operation and a read operation of the memory cell array. A first ground select line (GSL) region included in the first cell block includes a plurality of GSLs stacked in a vertical direction. One or more ground select transistors of a plurality of ground select transistors connected to each of the GSLs are programmed to a first threshold voltage and the other ground select transistors of the plurality of ground select transistors not connected to the GSLs are programmed to a second threshold voltage that is higher than the first threshold voltage. A first line included in the first GSL region in the first cell block is arranged at a same height as a word line connected to memory cells storing the user data in the second cell block.