The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

Jul. 21, 2023
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Xuan Tian, Shanghai, CN;

Liang Li, Shanghai, CN;

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/4096 (2006.01); G11C 11/408 (2006.01); G11C 11/4094 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4096 (2013.01); G11C 11/4085 (2013.01); G11C 11/4094 (2013.01);
Abstract

Technology is disclosed herein compensating for neighbor memory cell interference on a target memory cell when reading the target memory cell. The voltage that is applied to the bit line associated with the target memory cell may have a magnitude that depends on the data state of the neighbor memory cell. The magnitude of the voltage on the bit line may impact the amount of drain-induced barrier lowering (DIBL) experienced by the target memory cell. The amount of DIBL may be used to provide a desired amount of compensation for the neighbor memory cell interference. A higher bit line voltage may be used to create a greater amount of DIBL and therefore greater amount of compensation for neighbor memory cell interference.


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