The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 12, 2025
Filed:
Feb. 13, 2024
Cypress Semiconductor Corporation, San Jose, CA (US);
Rajagopal Narayanasamy, Bangalore, IN;
Ashwin Nair, Ernakulam, IN;
Sanat Kumar Mishra, Bangalore, IN;
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A system to perform high speed passive serial configuration of an FPGA is disclosed. The system includes an MCU that includes an interface, an FPGA coupled to the MCU over the interface, and a flash memory coupled to the MCU and to the FPGA over the interface. The flash memory includes MCU firmware for the MCU and FPGA configuration data for the FPGA. To perform passive serial configuration of the FPGA, the MCU is operable to at least: configure the flash memory to an input/output (IO) mode, place the FPGA in a configuration mode, send a read command over the interface to the flash memory for the FPGA configuration data, and continuously provide a clock signal over the interface to the flash memory until the FPGA configuration data is entirely read.