The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 2025

Filed:

Jun. 07, 2023
Applicant:

Infineon Technologies Canada Inc., Ottawa, CA;

Inventors:

Marco A Zuniga, Berkeley, CA (US);

Thomas William Macelwee, Nepean, CA;

Vineet Unni, Kanata, CA;

Claudio Andres Canizares, Morgan Hill, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/47 (2025.01); H03K 17/687 (2006.01); H10D 62/85 (2025.01); H10D 64/23 (2025.01);
U.S. Cl.
CPC ...
H10D 30/475 (2025.01); H03K 17/6871 (2013.01); H10D 62/8503 (2025.01); H10D 64/254 (2025.01);
Abstract

A transistor structure that includes multiple heterojunction layer sets, each generating a two-dimensional electron gas (2DEG), such that the transistor structure has a stack of 2DEGs that may be used to conduct between source and drain. A terminal is provided proximate an uppermost 2DEG to control whether the uppermost 2DEG is continuous between a source contact and a source plug. A source plug connects the uppermost 2DEG with the next 2DEG, and a drain plug also connects the uppermost 2DEG with the next 2DEG. Thus, the gate terminal may control the flow of current in sub-surface 2DEGs between the source and drain.


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