The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 2025

Filed:

Jun. 15, 2023
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Haibo Fei, San Diego, CA (US);

Xiahan Zhou, San Diego, CA (US);

Dongwon Seo, San Diego, CA (US);

Parisa Mahmoudidaryan, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/78 (2006.01); H03M 1/10 (2006.01); H03M 1/06 (2006.01); H03M 1/74 (2006.01);
U.S. Cl.
CPC ...
H03M 1/785 (2013.01); H03M 1/1023 (2013.01); H03M 1/06 (2013.01); H03M 1/0617 (2013.01); H03M 1/74 (2013.01);
Abstract

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) circuit. The DAC circuit generally includes: a decoder coupled to an input of the DAC circuit and current-steering cells coupled to an output of the decoder. Outputs of the current-steering cells may be coupled to a positive output node and a negative output node of the DAC circuit. The DAC circuit may also include an offset detection circuit including: a comparator having a first input and a second input selectively coupled to the positive output node and the negative output node; and a digital controller having an input coupled to an output of the comparator and an output coupled to the decoder. In some aspects, the DAC circuit includes one or more calibration DACs coupled to the offset detection circuit.


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