The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2025
Filed:
Mar. 10, 2023
Applicant:
Kioxia Corporation, Tokyo, JP;
Inventors:
Keisuke Nakatsuka, Kobe Hyogo, JP;
Yasuhiro Uchiyama, Yokkaichi Mie, JP;
Assignee:
Kioxia Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/528 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); H01L 23/522 (2006.01); H01L 25/18 (2023.01); H10B 41/10 (2023.01); H10B 41/20 (2023.01); H10B 43/10 (2023.01); H10B 43/20 (2023.01); H10B 80/00 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); H01L 23/5226 (2013.01); H01L 25/18 (2013.01); H10B 41/10 (2023.02); H10B 41/20 (2023.02); H10B 43/10 (2023.02); H10B 43/20 (2023.02); H10B 80/00 (2023.02);
Abstract
According to one embodiment, there is provided a semiconductor memory device including a first chip, a second chip and a third chip. In the first chip, plural first conductive layers are stacked via a first insulating layer. In the second chip, plural second conductive layers are stacked via a second insulating layer. A number of stack layers in the plural first conductive layers and a number of stack layers in the plural second conductive layers are different from each other.