The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 2025

Filed:

Jun. 06, 2022
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Zheng Tao, Heverlee, BE;

Stefan Decoster, Bertem, BE;

Assignee:

IMEC VZW, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/3213 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/32139 (2013.01); H01L 21/76837 (2013.01); H01L 21/76883 (2013.01); H01L 23/5226 (2013.01); H01L 23/53252 (2013.01);
Abstract

A method for forming an interconnection structure () for a semiconductor device is disclosed, wherein a first conductive layer is etched to form a set of third conductive lines () above a first and second conductive line (). At least one of the third conductive lines comprises a contacting portion forming a first via connection () to the second conductive line. The method further comprises forming spacers () on side walls of the set of third conductive lines, and forming, between two neighboring spacers, a via hole () extending to the underlying first conductive line. A second conductive layer is deposited, filling the via hole to form a second via connection () and forming a set of fourth conductive lines () extending between the spacers.


Find Patent Forward Citations

Loading…