Secure processor performing user authentication, and electronic device including the same

Abstract

Electronic device including SoC which includes secure processor performing user authentication based on authentication data received from user, and nonvolatile memory device storing first event count is disclosed. The secure processor includes volatile memory that stores failure count increasing as the user authentication fails and being reset as the user authentication succeeds, security module that restricts the user authentication of the user during first time period when the failure count reaches first threshold value, and OTP memory that stores second event count increasing as throttle level corresponding to the failure count changes. When the user authentication succeeds and when power-off request for the system on chip is generated, the first event count is updated based on the second event count. When the secure processor is powered on after the SoC is powered on, the security module compares the first and second event count to determine whether sudden power-off occurs.