The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 2025

Filed:

Oct. 20, 2022
Applicant:

Lodestar Licensing Group Llc, Evanston, IL (US);

Inventor:

Hyun Yoo Lee, Boise, ID (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 13/00 (2006.01); G11C 29/02 (2006.01); G11C 29/50 (2006.01); H04L 25/02 (2006.01); H05K 1/02 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4086 (2013.01); G06F 13/00 (2013.01); G11C 29/022 (2013.01); G11C 29/023 (2013.01); G11C 29/028 (2013.01); G11C 29/50008 (2013.01); H04L 25/0278 (2013.01); H05K 1/0246 (2013.01); H05K 1/025 (2013.01); G11C 2207/2254 (2013.01);
Abstract

Methods, systems, and apparatuses related to memory operation with common clock signals are provided. A memory device or system that includes one or more memory devices may be operable with a common clock signal without a delay from switching on-die termination on or off. For example, a memory device may comprise first impedance adjustment circuitry configured to provide a first impedance to a received clock signal having a clock impedance and second impedance adjustment circuitry configured to provide a second impedance to the received clock signal. The first impedance and the second impedance may be configured to provide a combined impedance about equal to the clock impedance when the first impedance adjustment circuitry and the second impedance adjustment circuitry are connected to the received clock signal in parallel.


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