System memory address decoding for interleaving addresses across physical regions of a system-on-chip (soc) and across shared memory resources in a processor-based system

Abstract

System memory address decoding for interleaving addresses across physical regions of a system on hip (SOC) and across shared memory resources in a processor based system and related hashing circuits are disclosed. In exemplary aspects, the SoC is configured to discover, for every range of addresses, the number of physical regions and the number and/or size of the shared memory resources available including caches, snoop filters and memory interfaces within each physical region. The SoC may include a system memory address decoding circuit that is configured to adaptively decode a memory address based on the memory address range in which the system address resides and then direct such memory access request to the proper shared memory resource so that each address in the memory address range spans across all of the shared memory resource in the range.