Image processing apparatus with multibank registers for storing source, destination, and setting information for operational circuits

Abstract

An image processing apparatus includes a central processing unit (CPU), an image processor, multiple bus masters, and a memory, all interconnected through a system bus. The image processor includes a control circuit executing a program stored in an embedded program memory that allows the CPU to write data. The image processor also includes operational circuits that perform specific operations on input data and produce operation results. The results are temporarily stored in internal memories. The apparatus includes registers that hold various information, input sources, output destinations, and setting information for each operational circuit. A selection circuit selects, based on the information of the registers, the memory, or the internal memories, as an input source of image data for each operational circuit and the memory, or one of the internal memories, as the output destination for the operation results.