The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 05, 2025

Filed:

Sep. 03, 2019
Applicant:

Drexel University, Philadelphia, PA (US);

Inventors:

Divya Pathak, Karnataka, IN;

Ioannis Savidis, Wallingford, PA (US);

Assignee:

Drexel University, Philadelphia, PA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 1/3234 (2019.01); G06F 1/324 (2019.01); G06F 1/3296 (2019.01); G06F 30/25 (2020.01); G06F 30/337 (2020.01); G06F 30/392 (2020.01); G06N 3/006 (2023.01); G05F 1/575 (2006.01); H02M 3/00 (2006.01);
U.S. Cl.
CPC ...
G06F 1/3296 (2013.01); G06F 1/324 (2013.01); G06F 1/3243 (2013.01); G06F 30/25 (2020.01); G06F 30/337 (2020.01); G06F 30/392 (2020.01); G06N 3/006 (2013.01); G05F 1/575 (2013.01); H02M 3/00 (2013.01);
Abstract

An on-chip voltage delivery method for a system includes multiple processor cores operating at multiple voltage levels. Distributed on-chip DC-DC converters as voltage regulators may deliver point of load current to the different units of a processor core operating at the same voltage level. Distributed timing sensors calibrated to generate digitized clock edge location. A power management unit may take input from the timing sensors, processes it through a particle swarm optimizer and generates digitized voltage identification code as reference to the distributed voltage regulators. The particle swarm optimizer may provide disparate voltage levels feasible for a given frequency of operation of the processor core with a provision to operate at multiple frequencies. The run-time assignment of the voltage through the particle swarm optimizer may negate the effects of transistor aging, process, temperature, and power supply noise induced variation in the load circuits, voltage regulators and sensors.


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