The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

Feb. 16, 2022
Applicant:

Powerchip Semiconductor Manufacturing Corporation, Hsinchu, TW;

Inventors:

Chien-Lung Wu, Hsinchu, TW;

Wen-Hao Huang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10F 39/18 (2025.01); H10F 39/00 (2025.01); H10F 39/12 (2025.01);
U.S. Cl.
CPC ...
H10F 39/807 (2025.01); H10F 39/014 (2025.01); H10F 39/024 (2025.01); H10F 39/18 (2025.01); H10F 39/199 (2025.01); H10F 39/8037 (2025.01); H10F 39/805 (2025.01); H10F 39/8067 (2025.01); H10F 39/811 (2025.01); H10F 39/8053 (2025.01); H10F 39/8057 (2025.01); H10F 39/8063 (2025.01);
Abstract

The disclosure provides an image sensor integrated chip and a method for forming the same. The image sensor integrated chip includes a substrate including a pixel region, an isolation structure disposed in the substrate and configured at opposite sides of the pixel region, an image sensing element disposed in the pixel region of the substrate, a gate structure disposed on the pixel region of the substrate, a first dielectric layer disposed above the pixel region of the substrate and covering sidewalls and a portion of a top surface of the gate structure, and a reflective layer disposed on the first dielectric layer. The reflective layer overlaps with the image sensing element and the portion of the top surface of the gate structure in a first direction perpendicular to a surface of the substrate.


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