The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

Sep. 07, 2022
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Keiji Hosotani, Yokkaichi Mie, JP;

Fumitaka Arai, Yokkaichi Mie, JP;

Hiroaki Kosako, Yokkaichi Mie, JP;

Takayuki Kakegawa, Yokkaichi Mie, JP;

Shinya Naito, Toyota Aichi, JP;

Ryo Fukuoka, Yokkaichi Mie, JP;

Kouji Matsuo, Ama Aichi, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 43/40 (2023.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/14 (2006.01);
U.S. Cl.
CPC ...
H10B 43/40 (2023.02); G11C 16/0466 (2013.01); G11C 16/08 (2013.01); G11C 16/14 (2013.01);
Abstract

A semiconductor memory device includes a memory cell array and a peripheral circuit. The peripheral circuit includes a plurality of first nodes disposed corresponding to a plurality of first via electrodes, a charging circuit that charges the plurality of first nodes, a discharging circuit that discharges the plurality of first nodes, an address select circuit that electrically conducts one of the plurality of first nodes with the charging circuit or the discharging circuit in response to an input address signal, a plurality of first transistors each disposed in a current path between two of the plurality of first nodes, and a plurality of amplifier circuits that are disposed corresponding to the plurality of first via electrodes and include input terminals connected to any of the plurality of first nodes and output terminals connected to any of the plurality of first via electrodes.


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