The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

Apr. 06, 2022
Applicant:

Imec Vzw, Leuven, BE;

Inventor:

Jan Van Houdt, Bekkevoort, BE;

Assignee:

IMEC vzw, Leuven, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 51/00 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01); H10B 51/20 (2023.01); H10B 51/30 (2023.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01);
U.S. Cl.
CPC ...
H10B 41/35 (2023.02); H10B 41/27 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 51/20 (2023.02); H10B 51/30 (2023.02); H10D 30/0415 (2025.01); H10D 30/701 (2025.01);
Abstract

The disclosed technology generally relates to memory structures, for example for a vertical NAND memory. In one aspect, a memory structure includes a substrate and a layer stack arranged on a surface of the substrate, wherein the layer stack includes one or more conductive material layers alternating with one or more dielectric material layers. The memory structure can also include a trench in the layer stack, wherein the trench is formed through the one or more conductive material layers, and wherein the trench includes inner side walls. The memory structure also includes a programmable material layer arranged in the trench and which covers the inner side walls of the trench. The memory structure further includes an oxide semiconductor layer arranged in the trench over the programmable material layer.


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