The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 29, 2025
Filed:
Apr. 06, 2022
Western Digital Technologies, Inc., San Jose, CA (US);
Qingbo Wang, Irvine, CA (US);
Mitchell Robert Fream, Germantown, MD (US);
Adarsha Balaji, Philadelphia, PA (US);
Martin Lueker-Boden, Fremont, CA (US);
Dejan Vucinic, San Jose, CA (US);
Western Digital Technologies, Inc., San Jose, CA (US);
Abstract
A mesh network-on-a-chip (NOC) with heterogenous routers for use with homogenous processing elements. Some of the routers are configured differently from other routers to interface more efficiently with particular physical resources that the processing elements require, such as particular input/output or memory devices. For example, one router is configured for use with the Peripheral Component Interconnect Express (PCIe) protocol, whereas another router is configured for use with the InterLaken communication protocol. Still further, the overall system is configured so that the various physical resources are physically adjacent to the particular router that is designed to access the resource to help ensure fair access by each processing element of the NOC to the particular resources that are required. The NOC may be part of a large manycore system on field programmable gate array (FPGA). The methods and apparatus described herein are generally applicable to all system-on-a-chip (SOC) designs.