The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

Dec. 15, 2022
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Ankita Paul, Bangalore, IN;

Lokesh Kumar Gupta, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/00 (2006.01); G06F 13/40 (2006.01); H03F 3/45 (2006.01); H04B 1/44 (2006.01); H04L 12/40 (2006.01);
U.S. Cl.
CPC ...
H04B 1/44 (2013.01); G06F 13/4072 (2013.01); H03F 3/45179 (2013.01); H03F 3/45668 (2013.01); H04L 12/40 (2013.01); H04L 2012/40215 (2013.01);
Abstract

Differential signaling transmitter circuitry includes upper and lower driver stacks, each with at least one upper blocking transistor and a bias transistor, further includes first and second control loops. A first control loop includes a replica stack including replicas of the bias transistor and blocking transistors of a first one of the driver stacks, and a second control loop includes replica stacks, one with replicas of the bias and blocking transistors of the upper driver stack and one with replicas of the bias and blocking transistors of the lower driver stack. One of the replica stacks in the second control loop receives an output from the first control loop. First and second switching circuitry couples outputs of the first and second control loops to gates of bias transistor in the upper and lower driver stacks, respectively, responsive to a data signal.


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