The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

May. 17, 2024
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventor:

Roman Ogirko, Lviv, UA;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 3/00 (2006.01); G06F 3/044 (2006.01);
U.S. Cl.
CPC ...
H03M 3/39 (2013.01); G06F 3/0446 (2019.05); G06F 2203/04111 (2013.01);
Abstract

An integrated circuit includes a sigma-delta modulator coupled to a receive electrode of a capacitive touch screen sensor and including a first single-ended integrator and a second single-ended integrator selectively coupled to an output of the first single-ended integrator. A latch is coupled to an output of the second single-ended integrator and driven by a frequency modulation signal. A balancing circuit is selectively coupled to a first input of the first single-ended integrator and to a second input of the second single-ended integrator. Logic is coupled to the balancing circuit and causes, based on the frequency modulation signal and an output value of the latch, the balancing circuit to one of: apply a positive balancing current to the first input and a negative balancing current to the second input; or apply a positive balancing current to the second input and a negative balancing current to the first input.


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