The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 29, 2025
Filed:
Aug. 02, 2023
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventor:
Atsushi Motozawa, Tokyo, JP;
Assignee:
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/02 (2006.01); H03K 5/133 (2014.01); H03K 5/135 (2006.01);
U.S. Cl.
CPC ...
H03K 5/02 (2013.01); H03K 5/133 (2013.01); H03K 5/135 (2013.01);
Abstract
A jitter cancellation circuit includes a clock buffer and a current control unit. The clock buffer inputs a clock outputted from a clock propagation element driven by a power supply voltage. Further, the clock buffer decreases with respect to a power supply voltage according to an increase in an operating current, while giving a delay time increased according to a decrease in the operating current to output the clock. The current control unit is configured to increase/decrease the operating current of the clock buffer in an opposite phase of a fluctuation component of the power supply voltage.