The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

Oct. 05, 2022
Applicant:

Graphcore Limited, Bristol, GB;

Inventors:

Stephen Felix, Bristol, GB;

Phillip Horsfield, Bristol, GB;

Simon Jonathan Stacey, Bristol, GB;

Assignee:

GRAPHCORE LIMITED, Bristol, GB;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); G01R 31/317 (2006.01); G01R 31/3185 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); G01R 31/31716 (2013.01); G01R 31/318511 (2013.01); G01R 31/318536 (2013.01); G01R 31/318547 (2013.01); G01R 31/318555 (2013.01); G01R 31/318572 (2013.01); G01R 31/318597 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/94 (2013.01); H01L 25/50 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/80894 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06589 (2013.01); H01L 2225/06596 (2013.01); H01L 2924/1011 (2013.01); H01L 2924/1431 (2013.01);
Abstract

The first logic wafer is attached to a supporting wafer, which adds sufficient depth to this bonded structure such that the first logic wafer may be thinned during the manufacturing process. The first logic wafer is thinned such that the through silicon vias may be etched in the substrate of the first logic wafer so as to provide adequate connectivity to a second logic wafer, which is bonded to the first logic wafer. The second logic wafer adds sufficient depth to this bonded structure to allow the supporting wafer to then be thinned to enable through silicon vias to be added to the supporting wafer so as to provide appropriate connectivity for the entire stacked structure. The thinned supporting wafer is retained in the finished stacked wafer structure and may comprise additional components (e.g. capacitors) supporting the operation of the processing circuitry in the logic wafers.


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