The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

Sep. 06, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Se-Ho You, Seoul, KR;

Ji-Yong Park, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49833 (2013.01); H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/16137 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32137 (2013.01); H01L 2224/73203 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/1511 (2013.01); H01L 2924/15151 (2013.01);
Abstract

A semiconductor package includes a first substrate including a first wiring layer inside the first substrate, a second substrate including a second wiring layer inside the second substrate, and a mold layer between the first substrate and the second substrate. An upper surface of the mold layer is on a same plane as upper surfaces of the first substrate and the second substrate. The package includes a first connecting film on each of the upper surface of the first substrate and the upper surface of the second substrate, the first connecting film connecting the first substrate and the second substrate, and a first semiconductor chip on the upper surface of the first substrate. The first semiconductor chip is spaced apart from the first connecting film, and an upper surface of the first connecting film is lower than an upper surface of the first semiconductor chip.


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