The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 29, 2025

Filed:

May. 10, 2023
Applicants:

Commissariat À L'énergie Atomique ET Aux Énergies Alternatives, Paris, FR;

Université D'aix-marseille, Marseilles, FR;

Centre National DE LA Recherche Scientifique, Paris, FR;

Inventors:

Djohan Bonnet, Grenoble, FR;

Tifenn Hirtzlin, Grenoble, FR;

Elisa Vianello, Grenoble, FR;

Eduardo Esmanhotto, Grenoble, FR;

Jean-Michel Portal, Saint Savournin, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/08 (2006.01); G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G11C 13/004 (2013.01); G11C 13/0097 (2013.01);
Abstract

A memory cell, includes first and second main terminals, an auxiliary terminal; M memristor(s) between the main terminals, M≥1; M primary switch(es), each in parallel with a memristor; and a secondary switch between the second main terminal and the auxiliary terminal. It is configured for writing to at least one memristor by opening each primary switch in parallel with the at least one memristor, closing each other primary switch, closing the secondary switch and applying a corresponding programming voltage between the first main terminal and the auxiliary terminal; and for reading at least one memristor by opening each primary switch in parallel with the at least one memristor, closing each other possible primary switch, opening the secondary switch and measuring a corresponding electrical quantity between the main terminals.


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