The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 29, 2025
Filed:
Mar. 27, 2024
Applicant:
Longitude Licensing Limited, Dublin, IE;
Inventor:
Chikara Kondo, Tokyo, JP;
Assignee:
LONGITUDE LICENSING LIMITED, Dublin, IE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G06F 13/16 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 11/4063 (2006.01); G11C 11/4072 (2006.01); G11C 11/4076 (2006.01); G11C 11/408 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4093 (2013.01); G06F 13/161 (2013.01); G11C 7/1045 (2013.01); G11C 7/109 (2013.01); G11C 7/1093 (2013.01); G11C 7/222 (2013.01); G11C 11/4063 (2013.01); G11C 11/4072 (2013.01); G11C 11/4076 (2013.01); G11C 11/4087 (2013.01); G11C 11/4096 (2013.01); Y02D 10/00 (2018.01);
Abstract
A method for writing a mode register in a semiconductor device, the method includes receiving a mode register command and a mode signal; generating a first mode register setting signal; delaying the first mode register setting signal in a first latency shifter to provide a second mode register setting signal; receiving a data signal in synchronization with the second mode register setting signal; and writing the mode signal to the mode register only if the received data signal has a first logic level.