Memory device adjusting skew of multi-phase clock signals, memory controller controlling the memory device, and operating method of the memory device

Abstract

A memory device includes a multi-phase clock generator configured to generate first to N-th clock signals having N different phases based on a clock signal from the memory controller, and a monitoring clock signal generator configured to generate a monitoring clock signal having a logic state corresponding to a data pattern in synchronization with edges of the first to N-th clock signals, wherein the monitoring clock signal includes a first monitoring clock signal configured to detect a skew between the first and third clock signals in a first step of a training operation, a second monitoring clock signal configured to detect a skew between the second and fourth clock signals in a second step of the training operation, and a third monitoring clock signal configured to detect a skew between the first and second clock signals in a third step of the training operation.